1. Field of the Invention
The present invention relates to a semiconductor memory device from which data can be read at high speed, and more particularly to a semiconductor memory device of single-bit line output type, such as a nonvolatile semiconductor memory device.
2. Description of the Related Art
FIG. 1 illustrates the data-reading section of a known nonvolatile semiconductor memory (EPROM) of single-bit line output type. As is shown in this figure, the memory cell array 11 of the EPROM comprises memory cells MC11, MC12, ... MC21, MC22, ... each memory cell comprises a floating-gate MOSFET and the memory cells are arranged in rows and columns. The drains of the memory cells MC of each column are connected to a bit line (BL1, BL2, ...). The source of every memory cell MC is connected to the ground Vss. The control gates of the cells MC of each row are connected to a word line (WL1, WC2, ...). The word lines WL1, WL2, ... are connected to a row decoder (not shown), thereby to receive the signals output from the row decoder.
The memory cell array further comprises a Y selector having N-channel MOS transistors 12-1, 12-2. The current paths of these MOS transistors are connected at one end to the bit lines BL1, BL2, ..., and at the other end to each other. The gates of the MOS transistors 12-1, 12-2 .... are connected to a column decoder (not shown) to receive the signals output from the column decoder. The cell array also has an N-channel charging MOS transistor 13A, an N-channel clamping MOS transistor 14A, a sense line 15A, and a P-channel load MOS transistor 16A. The current path of the charging MOS transistor 13A is connected between a power supply vcc and the node of the MOS transistors 12-1, 12-2, ... of the Y selector. The current path of the clamping MOS transistor 14A is connected the node of the MOS transistors 12-1, 12-2, ... and one end of the sense line 15A. The current path of the P-channel load MOS transistor 16A is connected between the sense line 15A and the power supply Vcc. The gate of the MOS transistor 16A is connected to the sense line 15A.
The EPROM further comprises a dummy cell DMC, a dummy bit line DBL, an N-channel MOS transistor 12D, an N-channel charging MOS transistor 13B, an N-channel clamping MOS transistor 14B, a reference line 15B, and a P-channel load MOS transistor 16B. The source and control gate of the dummy cell DMC are connected to the ground Vss and the power supply Vcc, respectively. The dummy cell DMC is of the same size as the memory cells MC as in the case of most nonvolatile semiconductor memories. The drain of the dummy cell DMC is connected by the dummy bit line DBL to the source of the N-channel MOS transistor 12D which has the same size as the MOS transistors 12-1, 12-2 ... of the Y selector. The gate of the MOS transistor 12D is connected to the power supply Vcc. The current path of the charging MOS transistor 13B is connected between the drain of the MOS transistor 12D and the power supply Vcc. The current path of the N-channel clamping MOS transistor 14B is coupled between the drain of the MOS transistor 12D and one end of the reference line 15B. The current path of the load MOS transistor 16B is connected between the reference line 15B and the power supply vcc. The gate of the load MOS transistor 16B is connected to the reference line 15B. The load MOS transistor 16B has a conductance greater than that of the load MOS transistor 16A, whereby a potential difference is present between the sense line 15A and the reference line 15B.
As is shown in FIG. 1, the EPROM further comprises a differential amplifier 17 and a bias circuit 18. The bias circuit 18 applies a bias voltage vbb to the gates of the MOS transistors 13A, 14A, 13B, and 14B, thereby to suppress the writing errors which would otherwise be likely to occur while data is being read from the EPROM. By virtue of the bias voltage applied from the circuit 18, the potentials of the bit lines BL1, BL2, ... will not increase above 1.2V to 1.5V. The differential amplifier 17 has two inputs, which are connected to the other end of the sense line 15A and the other end of the reference line 15B, respectively. The differential amplifier 17 amplifies the difference between the potential of the sense line 15A and that of the reference line 15B, and produces an output representing this potential difference. The potential of the sense line 15A is the voltage which the load MOS transistor 16A has converted from the conductance of any memory cell MC selected. The potential of the reference line 15B is the voltage which the load MOS transistor 16B has converted from the conductance of the dummy cell DMC. Hence, the output of the amplifier 17 is proportional to the difference between the conductance of any selected memory cell MC and that of the dummy cell DMC.
Each memory cell MC stores a "0" bit if it has a cell current Imc of 0 .mu.A, or a "1" bit if it has a cell current Imc of 100 .mu.A. If any selected memory cell MC stores a "1" bit--that is, if electrons have been injected into the floating gate of the memory cell MC, the threshold voltage of the memory cell MC is high, and the conductance thereof is also high. In this case, the potential of the sense line 15A is higher than that of the reference line 15B. If the selected memory cell MC stores a "0" bit--that is, if no electrons have been injected into the floating gate of the memory cell MC, the threshold voltage of the cell MC is low, and the conductance thereof is also low. In this case, the potential of the sense line 15A is lower than that of the reference line 15B. In either case, the differential amplifier 17 amplifies the difference between the potentials of the lines 15A and 15B, thereby reading data from the selected memory MC.
The access speed of the circuit shown in FIG. 1 greatly depends on the time required to read data from a memory cell MC storing a "0" bit after data has been read from a memory cell MC connected to the same word line WL and storing a "1" bit. The "1" bit is read from the selected memory cell in the following manner. First, the word line WL, to which the target memory cell MC storing a "1" bit, is connected is selected. Then, a potential is applied to this word line WL. Next, the bit line BL to which the target memory cell MC is discharged to the ground potential, whereby the "1" bit is read from the memory cell MC. To read the "0" bit thereafter from a memory cell MC connected to the same word line WL, it takes much time to increase the potential of the bit line BL, to which this memory cell MC is connected, to a value equal greater than that of the reference line 15B.
FIG. 2 is a graph representing how the potentials of the bit line BL, the sense line 15A and the reference line 15B change with time. As this figure shows, the potential VBL of the bit line BL increases for time t1, from 0V to the value V1 determined by the bias voltage vbb applied from the bias circuit 18, and remains at this value v1 thereafter. The potential V15A of the sense line 15A increases in the same way as the potential VBL, for a period of time t1, and keeps increasing thereafter since it is not clamped by the bias voltage Vbb. Upon lapse of time t2, the potential V15A reaches the potential V15B of the reference line 15B. At this time the output data of the differential amplifier 17 changes from "1" to "0." The delay time t1 and the delay time t2 are determined mostly by Cv/i, where C is parasitic capacitance, v is a potential difference, and i is a current.
The capacitance C, which determines the delay time t1, is in turn determined by the parasitic capacitance of the bit line BL, the parasitic capacitance present between the semiconductor substrate and the drain region of the selecting MOS transistor 12, and the parasitic capacitance coupled to that input node of the amplifier 17 which is connected to the sense line 15A. The current i, which is another determinant of the delay time time t1, is the sum of the current is supplied from the load MOS transistor 16A and the current is supplied from the charging MOS transistor 13A. The potential difference V, i.e., the third determinant of the delay time t1, is the difference v1 between the ground potential and the potential VBL of the bit line BL. The parasitic capacitance of the bit line BL and that of the selecting MOS transistor 12 tend to increase in proportion to the storage capacity of the EPROM. The current il supplied from the load MOS transistor 16A is determined by the conductance of the memory cells MC, and therefore decreases in inverse proportion to the size of the memory cells MC.
The parasitic capacitance determining the delay time t2 is, in turn, determined by four determinants. These determinants are: the parasitic capacitance present between the semiconductor substrate and the gate electrode of the load MOS transistor 16A; the parasitic capacitance present between the semiconductor substrate and the drain region of the transistor 16A; the input capacitance of the differential amplifier 17; and the parasitic capacitance present between the semiconductor substrate and the drain region of the clamping MOS transistor 14A. The current i, which is the second determinant of the delay time t2, is the current il flowing the current path of the load MOS transistor 14A. The greater the dimensions of the clamping MOS transistor 14A, the larger the current Ill. Nevertheless, the delay time t2 cannot necessarily be shortened since the parasitic capacitance present between the semiconductor substrate and the drain region of the transistor 14A increases in proportion to the dimensions thereof.
As may be understood from the above, with the conventional EPROM it is difficult to shorten the delay time t1 or the delay time t2 to enhance the access speed, because of the parasitic capacitances increased and also because of the memory-cell conductance decreased due to the reduced dimensions of each memory cell.